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preliminary product information this document contains in formation for a new product. cirrus logic reserves the right to modify this product without notice. copyright ? cirrus logic, inc. 2011 (all rights reserved) cirrus logic, inc. http://www.cirrus.com CS1601 CS1601h digital pfc controller for electronic ballasts features & description ? low pfc system cost ? best-in-class thd ? digital emi noise shaping reduces conducted emi ? adaptive switching frequency control minimizes boost inductor size ? high efficiency due to zero-current switching ? integrated feedback compensation simplifies system design ? comprehensive safety features ? undervoltage lockout (uvlo) ? output overvoltage protection ? cycle-by-cycle current limiting ? input voltage brownout protection ? open/short loop protection for iac & ifb pins ? thermal shutdown ? pin placement similar to traditional boundary mode (crm) controllers applications & description ? led power supply/driver ? fluorescent ballasts ? hid ballasts overview the CS1601 and CS1601h are digital power factor correction (pfc) controllers designed to deliver the lowest pfc system cost in electronic ballast appl ications. the controller operates in a variable frequency discontinuous conduction mode (vf- dcm) with zero-current switching (zcs) optimized to deliver best-in-class thd and minimize the size and cost of magnetic components. the CS1601 operates at switching frequencies up to 70khz while the CS1601h operates at frequencies extending to 100khz. the vf-dcm control algorithm varies both duty cycle and frequency. this spreads the emi frequency spectrum, thus reducing conducted emi filtering requirements. in addition, the maximum switching frequency is reached at the peak of the ac input, which allows for use of a smaller, more cost-effective boost inductor. the feedback loop is closed through an integrated compensation network within the controller, eliminating the need for additional external com ponents. protection features such as overvoltage, overcurrent, open and short-circuit protection, overtemper ature, and brownout protect the system during abnormal transient conditions. ordering information see page 15. r1 r2 r3 r4 r7 r5 r6 8 1 d1 c1 c2 regulated dc output q1 ac mains br 1 br1 br 1 br1 CS1601 CS1601h gd zcd ifb gnd cs iac vdd l b 6 3 57 4 v dd stby 2 v rect v link jun ?11 ds931pp6
CS1601 2 ds931pp6 1. introduction figure 1. CS1601 block diagram the CS1601 digital power factor correction (pfc) control ic is designed to deliver the lowest system cost by reducing the total number of system com ponents and optimizing the emi noise signature, which reduces the conducted emi filter requirements. the CS1601 digital algorithm determines the behavior of the boost converter durin g startup, normal operation, and under fault conditions (overvoltage, overcurrent, and overtemperature). figure 1 illustrates a high-level block diagram of the CS1601. the pfc processor logic regulates the power transfer by using an adaptive digital algorithm to optimize the pfc active- switch (mosfet) drive signal duty cycle and switching frequency. the adaptive controller uses independent analog- to-digital converter (adc) channels when sensing the feedback and feedforward analog signals required to implement the digital pfc control algorithm. the ac mains rectified voltage (on pin iac) and pfc output link voltage (on pin ifb) ar e transformed by the pfc processor logic and used to generate the optimum pfc active-switch drive signal (gd) by calculating the optimal switching frequency and t on time on a cycle-by-cycle basis. an auxiliary winding is typically added to the pfc boost inductor to provide zero-current detection (zcd) information. the zcd acts as a demagnetization sensor used to monitor the pfc active-switching behavior and efficiency. the auxiliary voltage is normalized using an external attenuator and is connected to the zcd pi n, providing the CS1601 a mechanism to detect the va lley/zero crossings. the zcd comparator looks for the zero crossing on the auxiliary winding and switches when the auxiliary voltage is below zero. switching in the valley of the oscillation minimizes the switching losses and reduces emi noise. the pfc controller uses a current sensor for overcurrent protection. the boost inductor peak current is measured across an external resistor in the switching circuit on a cycle- by-cycle basis. an ov ercurrent fault is generated when the sense voltage applied to the cs pin exceeds a predefined reference voltage. the CS1601 includes a supervisor & protection circuit to manage startup, shutdown, and fault conditions. the protection circuit is designed to prevent output overvoltage as a result of load and ac mains transients. the pfc power converter main rectified voltage (v rect ) and output link voltage (v link ) are monitored for overvoltage faults which would lead to shutdown of the pfc controller. the pfc overvoltage protection is designed for au to-recovery, i.e. operation resumes once the fault clears. v z por + - v dd (on ) v dd(off) voltage regulator 8 vdd 5 zcd + - v zcd(th) 7 gd zero crossing detect 6 gnd ifb iac v dd t leb v dd 15 k 24 k 3 v dd 15 k 24 k 1 adc adc t zcb 4 cs 600 + - cs threshold + - cs clamp v cs(clamp ) v cs(t h) stby v dd 600 k 2 i ref i ref
CS1601 ds931pp6 3 2. pin description cs pfc current sense ifb link voltage sense zcd pfc zero-current detect gnd ground gd p fc g a te d r iv e r vdd ic supply voltage stby standby ia c rectifier voltage sense 4 3 2 1 5 6 7 8 8-lead soic figure 2. CS1601 pin assignments pin name pin # i/o description ifb 1in link voltage sense ? a current proportional to the output link voltage of the pfc is input into this pin. the current is measured with an adc. stby 2in standby ? a voltage below 0.8v puts the ic into a non-operating, low-power state. the input has an internal 600k ? pull-up resistor to the v dd pin. iac 3in rectifier voltage sense ? a current proportional to the rectified line voltage is input into this pin. the current is measured with an adc. cs 4in pfc current sense ? the current flowing in the pfc mosfet is sensed through a resistor. the resulting voltage is applied to this pin and digitized for use by the pfc computational logic to limit the maximum current through the power fet. zcd 5in zero-current detect ? boost inductor demagnetization se nsing input for zero-current detection (zcd) information. the pin is exte rnally connected to the pfc boost inductor auxiliary winding through an external resistor divider. gnd 6pwr ground ? common reference. current return fo r both the input signal portion of the ic and the gate driver. gd 7out pfc gate driver ? the totem pole stage is able to drive the power mosfet with a peak current of 0.5a source and 1.0a sink. v dd 8pwr ic supply voltage ? supply voltage of both the input signal portion of the ic and the gate driver. a storage capacitor is connected on this pin to serve as a reservoir for oper- ating current for the device, including the gate drive current to the power transistor. this pin is clamped to a maximum voltage (v z ) by an internal zener function.
CS1601 4 ds931pp6 3. characteristics and specifications 3.1 electrical characteristics typical characteristics conditions: t a =25c, v dd = 13v, gnd = 0v all voltages are measured with respect to gnd. unless otherwise specified, all current are positive when flowing into the ic. minimum/maximum characteristics conditions: t j = -40 to +125 c, v dd = 10v to 15v, gnd = 0v parameter condition symbol min typ max unit v dd supply voltage operating range after turn-on v dd 7.9 - 17.0 v turn-on threshold voltage v dd increasing v dd(on) 9.8 10.2 10.5 v turn-off threshold voltage (uvlo) v dd decreasing v dd(off) 7.9 8.1 8.3 v uvlo hysteresis v hys -2.1-v zener voltage i dd =20ma v z 17.0 17.9 18.7 v v dd supply current startup supply current v dd =v dd(on) i st -6880 ? a operating supply current 3 CS1601 CS1601h c l = 1nf, fsw = 70khz c l =1nf, fsw=100khz i dd - - 1.5 1.75 1.7 1.95 ma ma standby supply current stby < 0.8v i sb -80112 ? a reference reference current i ref - 129 - ? a pfc gate drive output source resistance i gd = 100ma, v dd =13v r oh -9- ? output sink resistance i gd = -200ma, v dd =13v r ol -6- ? rise time 3 c l =1nf,v dd =13v t r -3245ns fall time 3 c l =1nf,v dd =13v t f -1525ns output voltage low state i gd = -200ma, v dd =13v vol - 0.9 1.3 v output voltage high state i gd = 100ma, v dd =13v voh 11.3 11.8 - v zero-current detection (zcd) zcd threshold v zcd(th) -50-mv zcd blanking t zcb - 200 - ns zcd sink/source current v zcd =50mv i zcd -2 -1 2 ma upper voltage clamp i zcd =1ma v clp -v dd -v overvoltage protection (ovp) ifb current at startup mode i ifb(startup) -116- ? a ifb current at normal mode i ifb(norm) - 129 - ? a ovp threshold i ref =129 ? ai ovp - 139 - ? a ovp hysteresis i ref =129 ? ai ovp(hy) -2- ? a
CS1601 ds931pp6 5 notes: 1. specifications guaranteed by design and are characterized and correlated using statistical process methods. 2. stby is designed to be driven by an open collector. the input is internally pulled up with a 600 k ? resistor. 3. for test purposes, load capacitance (c l ) is 1nf and is connected as shown in the following diagram. overcurrent protection (ocp) current sense reference clamp v cs(clamp) -1.0-v threshold on current sense v cs(th) -0.5-v leading edge blanking t leb - 300 - ns delay to output t cs - 60 350 ns brownout protection (bp) input brownout protection threshold gate drive turns off i bp(lower) -31.6- ? a input brownout recovery threshold gate drive turns on i bp(upper) -39.6- ? a thermal protection 1 thermal shutdown threshold t sd 134 147 159 c thermal shutdown hysteresis t sd(hy) -9-c stby input 2 logic threshold low - - 0.8 v logic threshold high v dd -0.8 - - v parameter condition symbol min typ max unit gd out gd gnd cs vdd buffer s 1 r 1 r 2 r 3 tp c l 1nf +15v -15v s 2 v dd
CS1601 6 ds931pp6 3.2 absolute maximum ratings notes: 4. the CS1601 has an internal shunt regulator that limits the voltage on the v dd pin. v z , the shunt regulation voltage, is defined in the vdd supply voltage section of the characteristics and specifications section on the previous page. 5. long term operation at the maximum junction temperature will result in reduced product life. derate internal power dissipation at the rate of 50mw/ c for variation over temperature. warning: operation at or beyond these limits may re sult in permanent damage to the device. normal operation is not guaranteed at these extremes. pin symbol parameter value unit 8v dd ic supply voltage v z v 1,3,4,5 - analog input maximum voltage -0.5 to v z v 1,3,4,5 - analog input maximum current 50 ma 7v gd gate drive output voltage -0.3 to v z v 7i gd gate drive output current -1.0 / +0.5 a -p d total power dissipation @ t a =50c 600 mw - ? ja junction-to-ambient thermal impedance 107 c/w -t a operating ambient temperature range 1 -40 to +125 c -t j junction temperature operating range -40 to +125 c -t stg storage temperature range -65 to +150 c all pins esd electrostatic discharge capability human body model machine model charged device model 2000 200 500 v
CS1601 ds931pp6 7 4. typical electrical performance -3.0% -2.5% -2.0% -1.5% -1.0% -0.5% 0.0% 0.5% -50 0 50 100 150 i ref drift temperature ( o c) figure 3. supply current vs. supply voltage figure 4. supply current (i sb , i st , i dd ) vs. temp figure 5. uvlo hysteresis vs. temp figure 6. turn-on & turn-off threshold vs. temp figure 7. reference current (i ref ) drift vs. temp 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -50 0 50 100 150 supply current (ma) temperature ( o c) start-up f sw(max) = 70khz f sw(max) = 100khz operating 0 1 2 3 -40 0 40 80 120 temperature ( o c) uvlo hysteresis temperature ( o c) 7 7.5 8 8.5 9 9.5 10 10.5 11 -60 -10 40 90 140 vdd (v) temperature ( o c) turn on turn off
CS1601 8 ds931pp6 0 2 4 6 8 10 12 14 -60 -40 -20 0 40 100 120 140 gate resistor (r oh , r ol ) temp ( o c) z out (ohm) source sink v dd = 13 v i source = 100 ma i sink = 200 ma 20 60 80 figure 8. gate resistance (r oh , r ol ) vs. temp figure 9. ovp vs. temp 96% 98% 100% 102% 104% 106% -50 0 50 100 150 v link (normalized at 25 o c) temperature ( o c) ovp normal 17 17.5 18 18.5 19 -50 0 50 100 150 v z (v) temperature ( o c) i dd = 20 ma figure 10. v dd zener voltage vs. temp
CS1601 ds931pp6 9 5. general description the CS1601 offers numerous features, options, and functional capabilities to the electronic product lighting designer. this digital pfc control ic is designed to replace legacy analog pfc controllers with minimal design effort. 5.1 pfc operation one key feature of the CS1601 is its operating frequency profile. figure 11 illustrates ho w the frequency varies over half cycle of the line voltage in steady-state operation. when power is first applied to the CS1601, it examines the line voltage and adapts its operating frequency to the line voltage as shown in figure 11. the operating frequency is varied from the peak to the trough of the ac input. during startup, the control algorithm generates ma ximum power while operating in critical conduction mode ( crm), providing an approximate square-wave current envelop within every half-line cycle. figure 11. switching frequency vs. phase angle figure 12 illustrates how the operating frequency of CS1601 (as a percentage of maximum frequency) changes with output power and the peak of the line voltage. figure 12. CS1601 max switching freq vs. output power figure 13 illustrates how the operating frequency of CS1601h changes with output power and the peak of the line voltage. figure 13. CS1601h max switching freq vs.output power when p o falls below 5%, the CS1601 changes to burst mode. (refer to burst mode section for more information.) the CS1601 is designed to function as a dcm controller. however, during peak periods, the controller may interchange control methods and operate in a quasi-critical-conduction mode (quasi-crm) at low line. for example, at 108vac main input under full load, the pfc controller will function as a quasi-crm controller at the peak of the ac line cycle, as shown in figure 14. figure 14. dcm and quasi-crm operation with CS1601 the zero-current det ection (zcd) of the boost inductor is achieved using an auxiliary winding. when the stored energy of the inductor is fully released to the output, the voltage on the zcd pin decreases, triggering a new switching cycle. this quasi-resonant switching allows the active switch to be turned on with near-zero inductor current, resulting in a nearly lossless switch event. this mi nimizes turn-on losses and emi noise created by the switching cycle. powe r factor correction control is achieved during light load by using on-time modulation. 0 20 40 60 80 100 120 04590135180 rectified line voltage phase (deg.) % of max switching freq. (% of max.) line voltage (% of max.) % p o max f sw m ax (kh z) 20 70 60 40 40 5 bu rst m ode 20 0 60 80 100 48 vin >156 vac (input voltage 108 ? 305 vac, v link = 460 v ) vin <182 vac (input voltage 108 ? 305 vac , v link = 460v) vin <158 vac ( input voltage 90 ? 264 vac, v link = 400 v) vin >136 vac (input voltage 90 ? 264 vac , v link = 400 v) % p o max f sw m a x (k hz) 100 75 burst mode 25 0 50 vin > 156 vac (input voltage 108 ? 305 vac , v link = 460v) vin < 182 vac (input voltage 108 ? 305 vac, v link = 460 v) vin < 158 vac (input voltage 90 ? 264 vac, v link = 400v) vin > 136 vac (input voltage 90 ? 264 vac , v link = 400v) 20 40 5 60 80 100 dcm quasi crm dcm quasi crm dcm i lb t [ms] i ac inductor current
CS1601 10 ds931pp6 5.2 startup vs. normal operation mode the CS1601 has two discrete operation modes: startup and normal. startup mode will be activated when v link is less than 90% of nominal value, v o(startup) and remains active until v link reaches 100% of nominal va lue, as shown in figure 15. startup mode is activated duri ng initial system power-up. any v link drop to less than v o(startup) , such as a load change, can cause the system to enter startup mode until v link is brought back into regulation. figure 15. startup and normal modes startup mode is defined as a surge of current delivering maximum power to the output re gardless of the load. during every active switch cycl e, the 'on' time is calculated to drive a constant peak current over th e entire line cycle. however, the 'off' time is calculated based on the dcm/ccm boundary equation. 5.3 burst mode burst mode is utilized to improve system efficiency when the system output power (p o ) is <5% of nominal. burst mode is implemented by intermittently di sabling the pfc over a full half-line period under light-load conditions, as shown in figure 16. figure 16. burst modes 5.4 output power and pfc boost inductor in normal operating mode, t he nominal output power is estimated by the following equation. where: p o rated output power of the system ? efficiency of the boost converter (estimated as 100% by the pfc algorithm) v in(min) minimum rms line voltage measured after the rectifier and emi filter. v in(min) is equal to 90vrms or 108vrms depending on the ac line voltage operating range. v link nominal pfc output voltage; v link = 400v when v in(min) =90vrms or v link = 460v when v in(min) = 108vrms f max maximum switching frequency; for the CS1601 f max = 70khz and the CS1601h f max = 100khz l b boost inductor specified by rated power requirement ??? margin factor to guarantee rated output power (p o ) against boost inductor tolerances. equation 1 is provided for expl anation purposes only. using substituted required design values for v link and f max gives the following equation: changing the value for the v link voltage is not recommended. solving equation 2 for the pfc boost inductor l b gives the following equation: if a value of the boost induct or other than that obtained from equation 3 above is used, the total output power capability as well as the minimum input voltage threshold will differ according to equation 2. note that if the input voltage drops below 108vrms and the inductance value is l b ?? l = l b l < l b ??
CS1601 ds931pp6 11 5.5 pfc output capacitor the value of the pfc output capacitor should be chosen based upon voltage ripple and hold-up requirements. to ensure system stability with the digital controller, the recommended value of the capacitor is within the range of 0.25 ? f/watt to 0.5 ? f/watt with a v link voltage of 460v. 5.6 output ifb sense & input iac sense a current proportional to the pfc output voltage, v link , is supplied to the ic on pin ifb and is used as a feedback control signal. this current is compared against an internal fixed- value reference current. the adc is used to measure the magnitude of the i ifb current through resistor r ifb . the magnitude of the i ifb current is then compared to an internal reference current of (i ref ) 129 ? a. figure 18. ifb input pin model resistor r ifb sets the feedback current and is calculated as follows: by using digital loop compensation, the voltage feedback signal does not require an ex ternal compensation network. a current proportional to the ac input voltage is supplied to the ic on pin iac and is used by the pfc control algorithm. figure 19. iac input pin model resistor r iac sets the iac current and is derived as follows: for optimal performa nce, resistors r iac & r ifb should use 1% tolerance or better resistors for best v link voltage accuracy. 5.7 valley switching the zero-current detection (zcd) pin is monitored for demagnetization in the auxiliar y winding of the boost inductor (l b ). the zcd circuit is designed to detect the v aux valley/zero crossings by sensing the voltage transformed onto the auxiliary winding of l b . figure 20. zcd input pin model the objective of zero-voltage switching is to initiate each mosfet switching cycle when it s drain-source voltage is at the lowest possible voltage potential, thus reducing switching losses. CS1601 uses an auxiliary winding on the pfc boost inductor to implement zero-voltage switching. figure 21. zero-voltage switch during each switching cycle, when the boost diode current reaches zero, the boost mosfet drain-source voltage begins oscillating at the resonant frequency of the boost inductor and mosfet parasitic output capa citance. the zcd_below_zero signal transitions from high to low just prior to a local minimum of the mosfet drain-source voltage oscillation. the zero- crossing detect circuit ensures that a zcd_below_zero pulse will only be generated when the comparator output is continuously high for a nominal time period (t zcb ) of 200ns. therefore, any negative edges on the comparator's output due to spurious glitches wi ll not cause a pulse to be generated. due to the CS1601's variable-frequency control, the mosfet switching cycle will not always be initiated at the first resonant ifb vdd 15 k 8 v link CS1601 24 k adc r5 r ifb i fb r6 1 r ifb v link v dd ? i ref ----------------------------- 460v v dd ? 129ma ------------------------------- == [eq.4] r1 r iac i ac ia c vdd 15 k 8 v rect CS1601 24 k adc r2 3 r iac r ifb = [eq.5] r3 i au x v link zc d l b r4 CS1601 zcd_below_zero d2 fe t drain n:1 + v aux - demag comparator + - v th( zcd) 5 i zcd c p zcd zero crossing detection gd ?on? zcd_below _zero
CS1601 12 ds931pp6 table below depicts approximate values for r3 and r4 for a range of boost-to-auxiliary inductor turns ratio, n. table 1. aux inductor turns ratio vs. r3 and r4 resistors r3 and r4 were calculated using v link = 460v and c p =10pf. equation 6 is used to calculat e the cut-off frequency defined by the rc circuit at the zcd pin. where: f c the cut-off frequency, f c , needs to be 10x the ringing frequency. c p capacitance at the zcd pin 5.8 brownout protection the CS1601 brownout detection circuit monitors the peak of the v rect input voltage and disables the pwm switching when it drops below a pre-determined threshold. hysteresis and minimum detection time are provided to avoid brownout detection during short input transients. when brownout is detected, the CS1601 enters standby mode. on recovery from brownout, it re-enters normal operating mode. current i ac is proportional to the ac input voltage v rect ,where v rect =r iac xi ac and r iac = r1+r2 in figure 19 on page 11. the digitized current applied to the iac pin is monitored by the brownout protection algorithm. when v rect drops below the brownout detection threshold, the CS1601 triggers a timer. the ic asserts the brownout protection and stops the gate- drive switching only if the time r exceeds 56ms. this is the equivalent of 7 rectified line cycles at 60hz. during the brownout state, the device continues monitoring the input line voltage. the device exits the brownout state when i ac exceeds the brownout upper threshold for at least 56ms. typical values for the lower (i bp(lower) ) and upper (i bp(upper) ) brownout thresholds are 31.6 ? a and 39.6 ? a, respectively. the overpower protection may activate prior to brownout protection, depending on the load. figure 22. brownout sequence the maximum response time of the brownout protection feature occurs at light-load co nditions. it is calculated by equation 7. where: v bp(th) brownout threshold voltage, v bp(th) = i bp(lower) xr iac 5.9 overvoltage protection the overvoltage protection (ovp) will trigger immediately and stop the gate drive when the current into the ifb pin (i ovp ) exceeds 105% of the reference current (i ref ) value. the ic resumes gate drive switching when the measured current at ifb drops below i ovp ?i ovp(hy) . equation 8 is used to calculate the ovp threshold (v ovp ). 5.10 overcurrent protection to limit boost inductor current through the fet and to prevent boost inductor saturation conditions, the CS1601 incorporates a cycle-by-cycle peak inductor current limit circuit using an external shunt resistor to ?s ense? the fet source current accurately. the overcurrent protection (ocp) circuit is designed to monitor the current when the active switch is turned on. the ocp circuit is enabled after the leading-edge blanking time (t leb ). the shunt voltage is compared to a reference voltage, v cs(th) , to determine whether an overcurrent condition exists. the ocp circuit triggers immediately, allowing the ocp algorithm to turn off the gate driver. the overcurrent protection circuit is also designed to monitor for a catastrophic overcurrent occurrence by sensing sudden and abnormal operating currents. a second ocp threshold, v cs(clamp) , determines whether a severe overcurrent condition exists. this immediately turns off the gate drive and the system enters a restart mode. the CS1601 inhibits all switching operations for approximately 1.6ms then attempts to restart normal operation. n~r3~r4 946k ? 1.75k ? 10 42k ? 1.75k ? 11 37.5 k ? 1.75k ? 12 35.5k ? 1.75k ? 13 32k ? 1.75k ? 14 29.5k ? 1.75k ? 15 27.5k ? 1.75k ? f c 12 ? r3 r4 ?? ?? c p ?? ? = [eq.6] 56 ms 56 ms start timer enter standby exit standby upper lower brownout thresholds start timer t brownout t brownout 8ms 8ms 5v ------------ 128 v v bp th ?? ? ?? 56 ms ++ = [eq.7] 8 = 8 5 -- - 128 94.8 ? ?? 56 ++ 117ms = v ovp r ifb i ovp ? v dd + = [eq.8]
CS1601 ds931pp6 13 5.11 overpower protection the CS1601 incorporates an internal overpower protection (opp) algorithm. this provi des protection from overload conditions. this algorithm us es the condition that output power is a function of the boost inductor (section 5.4). under moderate overload, v link may droop up to 10% while maintaining rated power and pfc. further increasing the load current causes v link to drop below the startup threshold (~360v). below this threshold, the circuit changes its operating mode to startup with more power available to raise v link . as v link reaches its nominal value, startup mode is canceled and power is now limited to the rated value. if the overload is still present, this cycle will repeat. if a sustained overload, or a repeated cycle of overload events is detected for greater than 112 ms, the CS1601 shuts down for 2.5 seconds, then attempts to restart. 5.12 open/short loop protection if the pfc output sense resistor, r ifb , fails (open or short to gnd), the measured output voltage decreases at a slew rate of about 2 v/ ? s, which is determined by the adc sampling rate. the ic stops the gate drive when the measured output voltage is lower than the measured line voltage. the ic resumes gate drive switching when the current into the ifb pin becomes larger than or equal to the current into the iac pin and v link is greater than the peak of the line voltage (v rect(pk) ). the maximum response time of open/short loop protection for r ifb is about 150 ? s. if the pfc input sense resistor r iac fails (open or short to gnd), the current reference signal supplied to the ic on pin iac falls to zero. 5.13 internal overtemperature protection an internal thermal sensor triggers a shutdown when the temperature exceeds 135c (n ominal) on the silicon. the sensor sends a signal to the core that supplies current to all internal digital logic, cutting off power from them. once the temperature of the ic has dr opped by 9c (nominal), the sensor resets, allowing power to the logic. 5.14 standby (stby ) function the standby (stby ) pin provides a means by which an external signal can cause the CS1601 to enter a non- operating, low-power state. the stby input is intended to be driven by an open-collector/open-drain device. internal to the pin, there is a pull-up resi stor connected to the v dd pin as shown in figure 23. since the pull-up resistor has a high impedance, the user may need to provide a filter capacitor (up to 1000pf) on this pin. figure 23. stby pin connection when the stby pin is not used, it is recommended that the pin be tied to v dd (pulled high). < 1 nf 600 k see text vdd stby gnd CS1601 8 6 2
CS1601 14 ds931pp6 5.15 summary of equations eq. # equation variables/recommended values 1 output power ( page 10 ) p o rated output power of the system. ? efficiency of the boost converter (estimated as 100% by the pfc algorithm). v in(min) minimum rms line voltage is 90vrms, measured after the rect ifier and emi filter. v link nominal pfc output voltage must be 400v. f max maximum switching frequency is 70khz. l b boost inductor specified by rated power requirement. ? margin factor to guarantee rated output power (p o ) against boost inductor tolerances. r iac value of the iac pin sense resistor(s). r ifb value of the ifb pin sense resistor(s). i ref value of the fixed, internal reference current. f c the cut-off frequency, f c , needs to be 10x the ringing frequency or f c = 10mhz. c p capacitance at the zcd pin. c p <10pf. v bp(th) brownout threshold voltage. v bp(th) = 94.8v. c out value of the output capacitor in microfarads. f line(min) minimum line frequency. v dd ic supply voltage. v ovp ovp threshold. i ovp current into the ifb pin. 2 output power w/ recommended values ( page 10 ) 3 boost inductor ( page 10 ) 4 output ifb sense resistor ( page 11 ) 5 input iac sense resistor ( page 11 ) 6 auxiliary winding cut-off frequency ( page 12 ) 7 maximum response time for brownout : ( page 12 ) 8 overvoltage protection ( page 12 ) 9 boost inductor peak current 10 boost inductor rms current 11 v link voltage ripple p o ?? v in min ?? ?? ? 2 ? v link v in min ?? 2 ? ?? ? 2f max l b v link ? ? ? --------------------------------------------------------- ? = p o ?? 90vrms ?? ? 2 ? 400v 90vrms 2 ? ?? ? 270khz l b 400 v ? ? ? ------------------------------------------------------------ - ? = l b ?? 90vrms ?? ? 2 ? 400v 90vrms 2 ? ?? ? 270khzp o 400 v ? ? ? ------------------------------------------------------------ - ? = r ifb v link v dd ? i ref ----------------------------- 400v v dd ? 129 ? a ------------------------------- == r iac r ifb = f c 12 ? r3 r4 ?? ?? c p ?? ? = t brownout 8ms 8ms 5v ------------ 128 v v bp th ?? ? ?? 56 ms ++ = v ovp r ifb i ovp ? v dd + = i lb pk ?? 4p o ? ? v ? in min ?? 2 ? ------------------------------------------- - = i lb rms ?? p o v in min ?? ? ? ------------------------------ = ? v link rip ?? p o 2 ? f line min ?? ? v link ? c out ? ------------------------------------------------------------------------ =
CS1601 ds931pp6 15 6. package drawing 7. ordering information 8. environmental, manufacturi ng, & handling information 8l soic (150 mil body) package drawing d h e e b a1 a c l ? seating plane 1 inches millimeters dim min max min max a 0.053 0.069 1.35 1.75 a1 0.004 0.010 0.10 0.25 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.19 0.25 d 0.189 0.197 4.80 5.00 e 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 h 0.228 0.244 5.80 6.20 l 0.016 0.050 0.40 1.27 ? 0 8 0 8 jedec # ms-012 part # temperature range package description CS1601-fsz -40 c to +125 c 8-lead soic, lead (pb) free model number peak reflow temp msl rating a a. msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. max floor life b b. stored at 30c, 60% relative humidity. CS1601-fsz 260 c 2 365 days
CS1601 16 ds931pp6 9. revision history revision date changes pp1 nov 2010 preliminary release - updated block diagram and general description sec- tion. pp2 dec 2010 updated brownout protection section, overcurrent protection section. added current sense reference clamp specification. pp3 jan 2011 updated stby pin and description. pp4 apr 2011 updated characteristics and specifications section. pp5 may 2011 updated typical electrical performance section. pp6 jun 2011 updated characteristics and specifications section. contacting cirrus logic support for all product questions and inqui ries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage ("critical applications"). cirr us products are not designed, au thorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life support products or other crit- ical applications. inclusion of cirrus products in such applic ations is unders tood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purp ose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer us es or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its office rs, directors, employees, distributors and other agents from any and all liability, includ- ing attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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